1) Why are the enable lines specifically used for connecting two or more IC packages in accordance to its application in decoder circuit?
a. It allows the reduction of digital function into similar function with more inputs & outputs
b. It allows the expansion of digital function into similar function with more inputs & outputs
c. It allows the reduction of digital function into different function with more inputs & outputs
d. It allows the expansion of digital function into different function with more inputs & outputs
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Answer
Explanation
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ANSWER: It allows the expansion of digital function into similar function with more inputs & outputs
Explanation:
No explanation is available for this question!
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2) The bus-request control input of micro-processor indicates the temporary suspension of current operation by driving all buses into________.
a. high impedance state
b. low impedance state
c. Both a & b
d. None of the above
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Answer
Explanation
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ANSWER: high impedance state
Explanation:
No explanation is available for this question!
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3) Which program controllable flipflop is in-built in microprocessor specifically used to set or clear the program instructions?
a. IEN flip-flop
b. IDN flipflop
c. SR flipflop
d. D flipflop
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Answer
Explanation
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ANSWER: IEN flip-flop
Explanation:
No explanation is available for this question!
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4) What kind of addressing resemble to direct- addressing mode with an exception of possessing 2- byte instruction along with specification of second byte in terms of 8 low - order bits of memory address?
a. Present- Page Addressing
b. Zero- Page Addressing
c. Relative Addressing
d. None of the above
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Answer
Explanation
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ANSWER: Zero- Page Addressing
Explanation:
No explanation is available for this question!
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5) Which parameter/s is/ are of relevant importance regarding the time interval of memory cycle specified by the microprocessor?
a. Internal clock frequency and access time
b. External clock frequency and access time
c. Internal as well as external clock frequencies
d. Only access time
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Answer
Explanation
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ANSWER: Internal clock frequency and access time
Explanation:
No explanation is available for this question!
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6) The boolean functions which can be represented by the sum of minterms and product of maxterms can be categorized in _______.
a. Standard form
b. Canonical form
c. Both a & b
d. None of the above
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Answer
Explanation
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ANSWER: Canonical form
Explanation:
No explanation is available for this question!
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7) Which gate must be interposed between the cascaded stages of a parallel binary adder comprising full adders for transmission purpose of carry C11 or C22 to the next stage?
a. OR gate
b. AND gate
c. EX-OR gate
d. NAND gate
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Answer
Explanation
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ANSWER: OR gate
Explanation:
No explanation is available for this question!
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8) The push and pop instructions belonging to the category of transfer instructions of microprocessor perform data transformation between _______.
a. two registers
b. processor register and memory stack
c. processor register and interface register
d. interface register and memory word
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Answer
Explanation
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ANSWER: processor register and memory stack
Explanation:
No explanation is available for this question!
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9) Which addressing mode execute its instructions within CPU without the necessity of reference memory for operands?
a. Implied Mode
b. Immediate Mode
c. Direct Mode
d. Register Mode
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Answer
Explanation
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ANSWER: Register Mode
Explanation:
No explanation is available for this question!
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10) What is/are the directional mode/s of shifting the binary information in a shift register?
a. Up-Down
b. Left-Right
c. Front-Back
d. All of the above
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Answer
Explanation
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ANSWER: Left-Right
Explanation:
No explanation is available for this question!
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